1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN).
2. Description of Related Art
With the progress of semiconductor technology, devices are gradually miniaturized to deep submicron level, or even smaller. Therefore, isolation between devices becomes quite important to avoid short circuit occurring between adjacent devices. Generally speaking, an isolating layer is formed between the devices, and the commonly used technique is local oxidation of silicon (LOCOS). However, LOCOS still has many defects including problems derived from the generation of stress, and Bird's Beak formed around the isolation structure which, among others, seriously obstructs the improvement of device integration. Therefore, the most commonly used method at present is shallow trench isolation (STI) process.
The method of fabricating the STI mainly includes forming a trench in a substrate and filling a dielectric material in the trench to serve as the isolating layer. Generally speaking, high density plasma (HDP) chemical vapor deposition (CVD) is usually used in this field for gap-filling of the isolating layer, and the dielectric material used is silicon dioxide (SiO2). However, as a process line width is reduced, an aspect ratio (AR) of the depth and width of the trench is increased accordingly. Thus, voids are generated during the gap-filling of the isolating layer, and the difficulty is also increased. Therefore, in the gap-fill process of STI of 90 nm and sub-90 nm, a multi-step gap-fill method of deposition-etch-deposition (DED) is developed to obtain an STI of high AR and without voids.
However, the multi-step gap-fill process has disadvantages that when switching from the etch step to the deposition step, serious gas phase nucleation (GPN) occurs due to the unstable plasma caused by the conversion of reaction gas. Consequently, due to the defect of GPN, the STI is projected and scratches products, thus reducing the reliability of the device, and the STI is liable to be attached on walls of a reaction chamber, thus causing contamination. Particularly, as the semiconductor process has reached nanometer level currently, a tolerance for contamination caused by the defect of GPN is much lower.